1. Field of the Invention
The present invention relates to a semiconductor device and particularly to a semiconductor device which outputs read data in synchronization with an external clock signal.
2. Description of Related Art
Recently, DDR (Double Data Rate) type synchronous memory device used as main memory of a personal computer or the like has been used in many cases as a semiconductor device which performs an operation in synchronization with a high-speed clock signal. For such semiconductor devices, a configuration in which output timing of read data is synchronized with an external clock signal is employed. According to this configuration, data transmission/reception between a controller and a semiconductor device can be performed at timing synchronized with the external clock signal. Therefore, data transmission/reception to each other is performed without an error. By the way, since internal delay is present in the semiconductor device itself, it is necessary to generate an internal clock signal inside the semiconductor device so that the output timing of the read data can be synchronized with the external clock signal while considering the delay time. The circuit realizing that is a DLL (Delay Locked Loop) circuit. Japanese Patent Application Laid-Open No. 2009-278528 discloses an example of such DLL circuit.
The trend of reduction of power consumption of semiconductor devices is increasing recently. Reduction in power consumption of the DLL circuit whose power consumption is said to be large in general can greatly contribute to lower power consumption of the semiconductor device. But on the other hand, since the trend of speeding-up of the semiconductor device is also increasing, improving the accuracy of timing control is becoming increasingly necessary. As a result, power consumption in the DLL circuit tends to be larger. The present invention has an object to provide a semiconductor device with highly accurate timing control while power consumption in such DLL circuit is suppressed.